Fully Digital Calibration of Time-Interleaved A/D Converter with Cascaded Higher-Order Sampling-Timing Correction

Although a sampling rate and a resolution of a time-interleaved A/D converter (ADC) have improved remarkably by recent advance of digital calibration, it is still difficult to achieve an effective resolution larger than 12 bits for sampling rate higher than 1 GS/s. This limitation is mainly caused by higher-order effect of sampling-timing mismatch among unit converters. To overcome the fundamental limitation, fully digital calibration of a time-interleaved ADC with cascaded higher-order sampling-timing correction is presented. In the proposed correction method, by using a reference ADC as an only additional analog component, analog tuning is eliminated, allowing mismatch effects to be corrected solely through post-digital processing. Due to its fully digital nature and unlimited correction in principle provided by the cascaded processing, accuracy is only limited by digital implementation cost, which is mitigated significantly with CMOS scaling. The extension to a sub-sampling time-interleaved ADC is also presented for a broad range of applications. Effectiveness of the proposed calibration was verified by extensive simulation with the 3rd-order sampling-timing correction for both standard and sub-sampling time-interleaved ADCs as well as measurement of a prototype time-interleaved ADC, which proved 11.5-bit effective resolution (71.2-dB SNDR) at 1GS/s with the 2nd-order correction.