Improved update rule for probabilistic computers

Ising machines realized on field-programmable gate arrays are used to solve combinatorial optimization problems. Performance is limited by the speed of the digital clocked arithmetic that is part of the algorithm, so in this study the authors simplify the Ising machine by replacing all arithmetic with a set of look-up tables, while retaining the polynomial scaling of chip resources with problem size. The result is reduction of both resource usage and time to solution by more than an order of magnitude, compared to previous approaches. Future implementations of Ising machines may be inspired by this simplified design.