A Hybrid SCVR With 4 × <i> <b>C</b> _F </i> Continuously Scalable-Conversion Ratio SC Stage

This work presents a hybrid switched-capacitor (SC) voltage regulator (VR) with a continuously scalable-conversion (CSC)-ratio stage implemented with off-chip flying capacitors (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {C}_{ F}$</tex-math> </inline-formula>s). By eliminating the need for high-density on-chip capacitors, this approach offers broader accessibility to designers. The use of off-chip <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {C}_{ F}$</tex-math> </inline-formula>s mandates minimizing the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {C}_{ F}$</tex-math> </inline-formula>s count to reduce I/O complexity, layout congestion, and routing overhead. However, this conflicts with the conventional CSC design philosophy for high efficiency, which implies many <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {C}_{ F}$</tex-math> </inline-formula>s. To resolve this tradeoff, we first propose clamping the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {C}_{ F}$</tex-math> </inline-formula> voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {V}_{ \text {CF}}$</tex-math> </inline-formula>) swing to 1/4 of its original range, achieving comparable efficiency and output power in the designs with full swing. The clamp is achieved via preceding SC stages, forming an SC-first configuration that improves the efficiency of the SC stages. Next, we propose a half-outphasing control that reduces the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {C}_{ F}$</tex-math> </inline-formula>s count to 4, while reconfiguring <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {V}_{ \text {CF}}$</tex-math> </inline-formula> steps to maintain high efficiency across a wide voltage conversion ratio (VCR) range. Moreover, we employ an SC<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>-CSC stage outphasing for more <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {V}_{ \text {CF}}$</tex-math> </inline-formula> steps, further improving efficiency. Fabricated in a 65-nm CMOS process, the prototype SCVR achieves a measured peak efficiency of 92.5% and a maximum output power of 1.52 W. With further advancements in process and packaging, this approach holds potential for higher output power and density.