Design and Analysis of a Low-Inductance DC-Link Busbar for 3.3kV SiC MOSFETs Using Partial Inductance Method and 3D FEM Validation

This study focuses on evaluating and estimating parasitic inductance in power electronic devices under fast switching conditions. As power converters aim for higher efficiency and performance, advanced technologies with shorter switching times—such as wide-bandgap (WBG) semiconductors—are increasingly used. These devices allow very high rates of current and voltage change (di/dt and dv/dt) in compact designs. However, their fast switching makes stray loop inductance more critical, often causing voltage overshoots that can affect device reliability and efficiency. Consequently, accurate determination of stray inductance, considering the size and geometry of the loop, is critical during the early stages of design. In this work, two distinct busbar loop structures are analyzed, and a design achieving minimized stray inductance along with optimal current distribution is proposed. An analytical methodology is developed based on the partial inductance approach, utilizing the concept of vector magnetic potential to provide an accurate estimation of magnetic field intensity and inductance values. The proposed analytical calculations are validated through finite element method (FEM) simulations conducted using ANSYS Q3D Extractor, allowing a direct comparison between the two busbar configurations. Furthermore, for experimental validation a double pulse test is perfromed with 3300V, 46A SiC MOSFET to confirm the accuracy and practical effectiveness of the proposed busbar layout.