MCExplorer: Exploring the Design Space of Multiple Compute-Engine Deep Learning Accelerators

Model-aware Deep Learning (DL) accelerators surpass generic ones in terms of performance and efficiency. These model-aware accelerators typically comprise multiple dedicated Compute Engines (CEs) to handle the varying computational characteristics of the operations within a DL model. Multiple-CE accelerators usually target Field-Programmable Gate Arrays (FPGAs), as FPGAs’ reconfigurability enables tailoring the CEs architectures to the varying computational characteristics of the model operations. The continuous evolution of DL models and their use in application domains with diverse optimization objectives, including low latency, high throughput, and energy efficiency, makes it challenging to identify highly optimized multiple-CE accelerator architectures. The design space of multiple-CE accelerators is vast, and the state of the art explores only limited parts of this space, which hinders the identification of accelerators with high performance and efficiency. To address this challenge, we propose a framework for exploring the design space of FPGA-based multiple-CE accelerators (MC E xplorer). MC E xplorer comprises a set of single and multiobjective optimization heuristics that target throughput, latency, energy efficiency, and tradeoffs among these metrics. MC E xplorer searches for optimized multiple-CE accelerator architectures given a DL model, a hardware resource budget, and a single or multiple objectives. MC E xplorer explores a space beyond that explored in the literature by not restricting the accelerator inter-CE arrangements and exploring distinct configurations of individual CEs. We evaluate MC E xplorer with various DL models and hardware resource budgets. The evaluation shows that by exploring a search space beyond that in the literature, MC E xplorer identifies highly optimized multiple-CE accelerators. These accelerators achieve up to 2.8× throughput improvement, 2.1× speedup, and 45% energy reduction compared to the state of the art. Moreover, the evaluation demonstrates that broad space exploration is key to identifying multiple-CE accelerators with the best performance-efficiency tradeoffs. MC E xplorer code is available at https://github.com/fqararyah/MCExplorer .

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Journal
ACM Transactions on Architecture and Code Optimization
Published
2025-11-06
DOI
https://doi.org/10.1145/3774913
Primary Topic
Embedded Systems Design Techniques
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article
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article

MCExplorer: Exploring the Design Space of Multiple Compute-Engine Deep Learning Accelerators

Pedro Trancoso, Mohammad Ali Maleki, Fareed Qararyah
ACM Transactions on Architecture and Code Optimization
Embedded Systems Design Techniques
article

MCExplorer: Exploring the Design Space of Multiple Compute-Engine Deep Learning Accelerators

Pedro Trancoso, Mohammad Ali Maleki, Fareed Qararyah
article en

Abstract

Model-aware Deep Learning (DL) accelerators surpass generic ones in terms of performance and efficiency. These model-aware accelerators typically comprise multiple dedicated Compute Engines (CEs) to handle the varying computational characteristics of the operations within a DL model. Multiple-CE accelerators usually target Field-Programmable Gate Arrays (FPGAs), as FPGAs’ reconfigurability enables tailoring the CEs architectures to the varying computational characteristics of the model operations. The continuous evolution of DL models and their use in application domains with diverse optimization objectives, including low latency, high throughput, and energy efficiency, makes it challenging to identify highly optimized multiple-CE accelerator architectures. The design space of multiple-CE accelerators is vast, and the state of the art explores only limited parts of this space, which hinders the identification of accelerators with high performance and efficiency. To address this challenge, we propose a framework for exploring the design space of FPGA-based multiple-CE accelerators (MC E xplorer). MC E xplorer comprises a set of single and multiobjective optimization heuristics that target throughput, latency, energy efficiency, and tradeoffs among these metrics. MC E xplorer searches for optimized multiple-CE accelerator architectures given a DL model, a hardware resource budget, and a single or multiple objectives. MC E xplorer explores a space beyond that explored in the literature by not restricting the accelerator inter-CE arrangements and exploring distinct configurations of individual CEs. We evaluate MC E xplorer with various DL models and hardware resource budgets. The evaluation shows that by exploring a search space beyond that in the literature, MC E xplorer identifies highly optimized multiple-CE accelerators. These accelerators achieve up to 2.8× throughput improvement, 2.1× speedup, and 45% energy reduction compared to the state of the art. Moreover, the evaluation demonstrates that broad space exploration is key to identifying multiple-CE accelerators with the best performance-efficiency tradeoffs. MC E xplorer code is available at https://github.com/fqararyah/MCExplorer .

ACM Transactions on Architecture and Code OptimizationVol. 22(4)
Chalmers University of Technology (SE), University of Gothenburg (SE)
Openalex Percentile: Top 64%
Embedded Systems Design Techniques
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