ORL-LO: Offline Reinforcement Learning for Pretraining and Finetuning in Logic Optimization
As a key step in digital integrated circuit (IC) design, logic synthesis involves various logic optimization algorithms, where the quality of results (QoR) depends heavily on the optimization sequence used. Exploring the optimization space is challenging as the number of potential optimal permutations grows exponentially. Traditional methods rely on manual adjustments by experts, but are difficult to deal with complex and different circuits, leading to significant optimality gaps. Many automatic methods have been introduced, but they still face problems of low generalization and low efficiency. In this work, we propose ORL-LO, a two-stage learning framework that leverages an offline reinforcement learning (RL) method (i.e., advantage-weighted actor-critic, AWAC) to pretrain on expert trajectories and finetune on target test circuits, enabling efficient exploration of optimal synthesis flows. Firstly, ORL-LO uses AWAC to pretrain a fast and high-performance intelligent policy to fully leverage the offline knowledge of a large corpus of high-quality expert trajectories. Then, the pretrained policy is finetuned for target circuits using AWAC and policy distillation to obtain better results. Compared with the state-of-the-art (SOTA) method, our framework can effectively improve the quality of logic optimization and significantly speed up the exploration time.
Authors
- Jianwang Zhai (ORCID: https://orcid.org/0000-0002-1581-3536)
- Kang Zhao (ORCID: https://orcid.org/0000-0003-0502-8523)
- Xiao Yang (ORCID: https://orcid.org/0009-0005-8340-9104)
- Chuan Shi (ORCID: https://orcid.org/0000-0002-3734-0266)
- Hongtao Cheng (ORCID: https://orcid.org/0009-0007-1527-621X)
- Guande Dong (ORCID: https://orcid.org/0009-0005-3570-4109)
Institutions
- Beijing University of Posts and Telecommunications (CN)
Publication Details
- Journal
- ACM Transactions on Design Automation of Electronic Systems
- Published
- 2025-11-06
- DOI
- https://doi.org/10.1145/3774323
- Primary Topic
- VLSI and FPGA Design Techniques
- Type
- article
- Field-Weighted Citation Impact
- 0.00