Prototyping Custom Hardware Performance Counters in gem5 Simulator: A Framework for RISC-V Side-Channel Attack Assessment

Authors

Institutions

Publication Details

Journal
SPIRE - Sciences Po Institutional REpository
Published
2025-06-30
Primary Topic
Cryptographic Implementations and Security
Type
article
Field-Weighted Citation Impact
0.00
Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

Prototyping Custom Hardware Performance Counters in gem5 Simulator: A Framework for RISC-V Side-Channel Attack Assessment

Muhammad Isa Khan, Maria Mushtaq, Ludovic Apvrille, Renaud Pacalet
SPIRE - Sciences Po Institutional REpository
Cryptographic Implementations and Security
article

Prototyping Custom Hardware Performance Counters in gem5 Simulator: A Framework for RISC-V Side-Channel Attack Assessment

Muhammad Isa Khan, Maria Mushtaq, Ludovic Apvrille, Renaud Pacalet
article en

Abstract

No abstract available for this paper.
SPIRE - Sciences Po Institutional REpository
Télécom Paris (FR), EURECOM (FR)
Openalex Percentile: Top 83%
Cryptographic Implementations and Security
Open Access PDFOpenAlex
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.

Prototyping Custom Hardware Performance Counters in gem5 Simulator: A Framework for RISC-V Side-Channel Attack Assessment — Muhammad Isa Khan, Maria Mushtaq, et al. · SPIRE - Sciences Po Institutional REpository (2025) | TGRS Research Map | TGRS