ANAQIN-X: A prototype low noise ASIC for the readout of highly dense semiconductor X-ray detectors

This article presents ANAQIN-X (Advanced Noise-optimized ASIC for Quantifying and Imaging in X-rays) a pixelated prototype readout chip dedicated to testing different architectures of Charge Sensitive Amplifiers (CSA), the first stage of the spectroscopic signal processing analog circuit. The chip is designed to read out low leakage current (1 pA), low capacitance (300 fF), hard X-rays detectors (Cd(Zn)Te/Si) in order to perform high-resolution (500 eV FWHM at 60 keV) hard X-ray (1-220 keV) spectroscopy. Its main block is a mini matrix of pixels of 250x250 µ m 2 designed in X-FAB’s 0.18 µ m CMOS technology. Each channel consumes 250 µW in nominal mode, and contains an optimized Charge Sensitive Amplifier (CSA) followed by a CR-RC shaper with tunable peaking time (from 144 ns up to 3.6 µ s) and a peak detector. The different CSA architectures integrated on this chip are based on continuous reset topology with nMOS or pMOS input transistors architectures with various W/L ratios. The chip includes also, an AC-coupled CSA with a tunable input capacitance (from 100 fF to 30 pF) and a Semi-AC coupling architecture allowing a reduction in the thermal noise generated by the reset transistor and the usage of small value coupling capacitance. The best performing pixel can reach a readout noise 20 el.rms without detector. A performance of 25 el.rms with a 300 fF detector can be considered. According to simulation, a noise reduction of 10 % is expected at 15 pA of leakage current, and a coupling capacitance of 1 pF is enough to get 98 % of gain. With an 300 fF input capacitor, the best performing pixel should be able to reach an Equivalent Noise Charge (ENC) of 21 el.rms.