The synthesis of two-dimensional materials for post-Moore integrated circuits

With the continuous scaling down of channel dimensions, the relentless miniaturization of CMOS-based integrated circuits is increasingly constrained by short-channel effects, leakage currents, and quantum tunneling phenomena, suggesting that Moore’s Law is approaching its physical limits. Two-dimensional (2D) materials, distinguished by their ultrathin nature, exceptional carrier mobility, and intrinsic passivation characteristics, offer a promising solution to mitigate short-channel effects while maintaining ultra-low leakage currents. Consequently, they are considered a viable pathway for further device miniaturization. In this review, we focus on 2D transistors, elaborating on recent advancements in synthesizing wafer-scale single-crystal 2D semiconductor materials, with particular emphasis on low-temperature (< 450 °C) synthesis techniques. Additionally, this review summarizes innovative strategies for synthesizing 2D dielectric layers that exhibit superior compatible with 2D semiconductor materials. Subsequently, this review discusses strategies to optimize the contact between 2D semiconductor materials and metal electrodes. Crucial advancements in 2D transistor technology, encompassing large-scale integration and unconventional device architectures, are also highlighted. Finally, this review delineates the major technical challenges and potential optimization directions for 2D transistors. This review is confident that resolving these bottlenecks will catalyze unprecedented advancements in post-Moore integrated circuit technology.