A 9.98-ENOB 8kHz Bandwidth 100-260 nW DT Level-Crossing ADC for Sparse and Generic Signals

This paper presents an event-driven Discrete-Time Level Crossing Analog-to-Digital Converter (DT-LCADC) that is energy-efficient in the conversion of both sparse and generic signals, and exploits signal sparsity to reduce the output data rate. The proposed DT-LCADC uses the comparator delay, to classify each level-crossing event as slow or fast, according to the rate of change of the input signal. The converter can adaptively select the most suitable search scheme, between linear and binary, according to the type of event. The proposed DTLCADC, manufactured with 65 nm CMOS technology, achieves 9.98 ENOB and a signal bandwidth of 8 kHz, while consuming between 100 and 260 nW from a 0.8 V supply, depending on the input signal. The corresponding Walden <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{F o M}_{W}$</tex> ranges from 6.2 to 16.1 fJ/c.s, achieving a more than 4 X improvement in worstcase power efficiency compared to state-of-the-art DT-LCADCs. To convert time-sparse neural signals, the proposed ADC requires only 110 nW, while reducing the output data rate down to 8.9 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{kb} / \mathrm{s}$</tex>. This leads to a compression ratio of 94.4%, compared to a Nyquist ADC with the same accuracy.