A 56-Gb/s PAM-4 Injection-Locked CDR

This paper reports an injection-locked clock and data recovery (CDR) circuit achieving 56-Gb/s PAM-4 for the first time, aimed at improving the jitter tolerance (JTOL) and locking range. To generate injection pulses for high-speed PAM-4 signals, the oscillator's output is used instead of the input data. To integrate this technique with a conventional phase locked loop (PLL)-based CDR including a bang-bang phase detector (BBPD), we activate the injection path only for large phase errors. This controlled self-injection into the LC oscillator allows the system to correct large phase errors with minimal disruption to the normal operation of the PLL-based loop, thus improving JTOL without affecting the jitter transfer (JTRAN). The added injection path improves the JTOL while employing two out of four phases of the quarter-rate clock for phase detection. Additionally, this injection path enhances the locking range of the CDR by counteracting cycle-slipping. Fabricated in a 28-nm bulk CMOS process, the proposed PAM-4 CDR achieves a JTOL value of 1-UI at 15 MHz, which represents a 50% improvement over existing solutions. The injection path contributes 65% to the JTOL improvement, while JTRAN remains unchanged with a bandwidth of 75 MHz. The measurements also indicate that enabling the injection path more than doubles the CDR's locking range. The power consumption of the proposed CDR is 35.8 mW, with less than 8% contributed by the added injection path.