An Area-Efficient and Low-Power Switched Capacitor Integrator for Discrete-Time Delta Sigma Modulators

This paper presents a novel switched-capacitor integrator for discrete-time delta-sigma modulators (DT-DSM) that eliminates the trade-off between integrator voltage gain and noise performance. By splitting the sampling capacitor and introducing a discharging phase into the circuit, the proposed architecture significantly reduces the required total capacitance. In addition to area reduction, the integrator dramatically decreases the current drawn from the reference node in DSMs, leading to a reduction in overall power consumption. As a proof of concept, a third order DT-DSM was implemented by incorporating the proposed integrator in a 180 nm CMOS technology, where the area required for implementing the first-stage capacitor array was reduced by 61.5% compared to a conventional integrator with the same performance. Measurement results show that the prototype achieves an SNR and SNDR of 104.9dB and 101.2dB, respectively, at fin <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$=66.185 ~\text{Hz}$</tex>.