Scaled Vertical Transport Gate-All-Around Nanostructured Channel (Nanosheet/Nanowire) Technology for Advanced CMOS Devices

This study explores a Gate-All-Around (GAA) architecture for 3nm and below nodes, introducing Vertical Transport (VT) GAA devices with nanostructured channels. We compare nanowire (NW) and nanosheet (NS) configurations, showcasing electrical performance, 3D logic cells, and design perspectives. Making the link from technology parameters to design performance metrics in a DTCO approach, we show that the VT-NS-FET device outperforms VT-NW-FETs and FinFETs, achieving up to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$50 x$</tex> improvement in terms of Energy-Delay Product (EDP) and up to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{1. 5 x}$</tex> improvement in terms of footprint. At the circuit level, we also demonstrate a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$7 x$</tex> footprint reduction of the VT-NS-FET implementation of a 2 -input XOR gate over a FinFET implementation, and a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2.8 x$</tex> reduction in output branch resistance over a VT-NW-FET implementation.