Efficient and Effective E-graph-based Logic Optimization

Recent efforts of applying e-graphs in logic synthesis have shown promising results. Nevertheless, e-graph-based gate-level logic optimization suffers from inefficiency and limited extraction quality. In this article, we propose a fast parallel e-matching algorithm for speeding up e-graph rewriting, and an efficient netlist extraction framework with high quality of results in both area and delay. Experiments show that e-graph rewriting can be accelerated by up to 8.3× over a high-performance e-graph library, and our extraction framework achieves 11.0% and 1.0% improvements in size and level on average, compared to the best results of the state-of-the-art netlist extraction method.

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Publication Details

Journal
ACM Transactions on Design Automation of Electronic Systems
Published
2025-11-05
DOI
https://doi.org/10.1145/3774883
Primary Topic
VLSI and FPGA Design Techniques
Type
article
Field-Weighted Citation Impact
0.00
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article

Efficient and Effective E-graph-based Logic Optimization

Bentian Jiang, Shiju Lin, Evangeline F. Y. Young, Guannan Guo et al.
ACM Transactions on Design Automation of Electronic Systems
VLSI and FPGA Design Techniques
article

Efficient and Effective E-graph-based Logic Optimization

Bentian Jiang, Shiju Lin, Evangeline F. Y. Young, Guannan Guo, Tianji Liu, Weihua Sheng, Nutdranai Jaruthikorn
article en

Abstract

Recent efforts of applying e-graphs in logic synthesis have shown promising results. Nevertheless, e-graph-based gate-level logic optimization suffers from inefficiency and limited extraction quality. In this article, we propose a fast parallel e-matching algorithm for speeding up e-graph rewriting, and an efficient netlist extraction framework with high quality of results in both area and delay. Experiments show that e-graph rewriting can be accelerated by up to 8.3× over a high-performance e-graph library, and our extraction framework achieves 11.0% and 1.0% improvements in size and level on average, compared to the best results of the state-of-the-art netlist extraction method.

ACM Transactions on Design Automation of Electronic SystemsVol. 31(2)
Chinese University of Hong Kong (HK), Huawei Technologies (China) (CN), Huawei Technologies (United States) (US), BioElectronics (United States) (US), University of Hong Kong (HK), South China University of Technology (CN)
Openalex Percentile: Top 68%
VLSI and FPGA Design Techniques
DOIOpen Access PDFOpenAlex
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Efficient and Effective E-graph-based Logic Optimization — Bentian Jiang, Shiju Lin, et al. · ACM Transactions on Design Automation of Electronic Systems (2025) | TGRS Research Map | TGRS