A compact hardware STBCS design by using stochastic computation

Abstract Chaotic systems play an indispensable role in the fields of cryptography and information security. Sine-Transform-Based Chaotic System (STBCS) can address the shortcomings of low complexity and limited chaotic behaviour of classical chaos systems. In this paper, a compact hardware STBCS is proposed and developed on the FPGA device by using the Stochastic Computation (SC) technique. The traditional arithmetic operations are replaced by the SC and finite state machines design. The structure of STBCS is optimised, where the disturbance method is employed to improve the chaotic behaviours and also taking the SC method into account for implementation. The hardware performance of the proposed design is verified via various tests of the chaotic system and corresponding random number generator. Experimental results show that the utilisation of the hardware resources is reduced especially the DSP components compared to the traditional design methods. This provides an efficient design for the random generator of the alternative cryptosystems.