High-Performance Unified Hardware Architecture for ML-DSA and ML-KEM PQC Standards

In response to the advent of quantum computers, which pose significant threats to traditional cryptographic systems, NIST announced the quantum-resistant Module Lattice-based Key Encapsulation Mechanism (ML-KEM) and Digital Signature (ML-DSA) standards in August 2024. While prior studies have proposed hardware designs to accelerate either ML-KEM or ML-DSA individually, a unified architecture supporting all requirements of both schemes remains lacking. Leveraging the shared lattice-based cryptographic structures of ML-KEM and ML-DSA, this paper proposes a novel, high-performance architecture that supports all phases of both standards. The design allows flexible switching between operation modes and security levels at runtime, providing versatility and user-friendliness. Based on a long-term analysis of both cryptosystem theories, we propose optimizations in unified components, with specific configurations that execute both schemes efficiently in hardware while reducing redundant resource utilization from overlapping tasks. The timing diagram is carefully arranged to maximize concurrency, allowing the architecture to deploy multiple tasks in parallel, thereby addressing performance bottlenecks commonly seen in asymmetric cryptosystems. Moreover, we integrate several efficient countermeasure techniques to mitigate side-channel attack vulnerabilities in the hardware implementation. The proposed architecture is validated through implementation on Zynq UltraScale+ FPGA platform, demonstrating optimal execution times for each main algorithm in both post-quantum cryptography standards. Compared to state-of-the-art designs, our implementation exhibits superior performance and efficiency, as evaluated by the area-time product metric, as well as solves problems arising from outdated standards in previous studies.