An On-Chip Circuit With Digital Output for Characterizing Transistor Current Mismatch Across Multiple Bias Conditions

This paper presents an on-chip measurement circuit with a digital output for characterizing local random variations in CMOS transistor currents and estimating the Pelgrom parameters, σ(<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V_th</i>) and σ(β)/β. The proposed circuit operates by selecting a transistor device under test (DUT) from an array, integrating it into a shared relaxation oscillator, and measuring the shift in its oscillation period due to a small change in the voltage swing. This enables precise measurement of the relative difference in transistor current, either between transistors in the array or under different biasing conditions for the same transistor. In addition, a mathematical approach using two-way analysis of variance (ANOVA) compensates for systematic offsets from peripheral circuits. A 0.18μm CMOS test chip with a 30 × 32 array demonstrates the effectiveness of the proposed method, yielding σ(<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V_th</i>) = 7.54 mV and σ(β)/β = 1.09%, with deviations of only 0.35 mV and 0.09 percentage point compared to direct current measurements.