Efficient Chip-Integrated Microfluidic Cooling Through Jet-Enhanced Manifold Microchannels

With the continuous miniaturization of logic and power electronics resulting in hotspot heat flux up to 1000 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{w}/\text{cm}^{2}$</tex>, ultra-high heat-flux dissipation has become the bottleneck of their performance in various applications. To address this challenge, we propose a novel jet-enhanced manifold microchannel (JMMC), with microchannels topologically optimized for improved cooling efficiency. The manifold configuration was optimized by numerical computation, and the microchannels was generated without a predefined structural topology. A regular pin-fin, and an optimized design were then manufactured by combining 3D printing and micro-fabrication, without the need for complex bonding or double-side etching process. Our experimental results indicate that the optimized layout can reduce the junction-to-fluid thermal resistance by 18%, and suppress the temperature gradients by over 44<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">%</sup> when compared to conventional pin-fin design. Further analysis demonstrates that the present cooling strategy achieves similar performance to state-of-art monolithic manifold microchannels with simpler architectures. The proposed optimized JMMCs could be easily scaled to large-footprint processors, and hold great potential for the thermal management of electronics.