Netlist-Aware Mixed-Cell-Height Legalization

Mixed cell heights pose significant challenges to placement in large-scale integrated circuits. In particular, the heterogeneity of cells remarkably complicates the legalization of mixed-cell-height cells. To preserve the global placement results as much as possible, we propose to directly optimize the total displacement through l1-norm minimization. For illegal cells that extend beyond the chip boundaries, the netlist information of cells is taken into account and a mixed-integer programming model is employed to determine the optimal placement that minimizes the half-perimeter wirelength (HPWL) variation. This joint optimization strikes a balance between minimizing geometric displacement and HPWL, ensuring that the legalization process remains compact to achieve better placement performance. Experimental evaluations on mixed-cell-height benchmarks demonstrate that the proposed approach achieves smaller total displacement and notably lower HPWL variation within practical time limits compared with state-of-the-art legalization methods. Moreover, this work provides a scalable foundation for future extensions to three-dimensional (3D) IC placement legalization.

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Publication Details

Journal
Electronics
Published
2025-10-31
DOI
https://doi.org/10.3390/electronics14214287
Primary Topic
VLSI and FPGA Design Techniques
Type
article
Field-Weighted Citation Impact
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article

Netlist-Aware Mixed-Cell-Height Legalization

Ting Liang, Bin Yih Liao, Weijie Chen
Electronics
VLSI and FPGA Design Techniques
article

Netlist-Aware Mixed-Cell-Height Legalization

Ting Liang, Bin Yih Liao, Weijie Chen
article en

Abstract

Mixed cell heights pose significant challenges to placement in large-scale integrated circuits. In particular, the heterogeneity of cells remarkably complicates the legalization of mixed-cell-height cells. To preserve the global placement results as much as possible, we propose to directly optimize the total displacement through l1-norm minimization. For illegal cells that extend beyond the chip boundaries, the netlist information of cells is taken into account and a mixed-integer programming model is employed to determine the optimal placement that minimizes the half-perimeter wirelength (HPWL) variation. This joint optimization strikes a balance between minimizing geometric displacement and HPWL, ensuring that the legalization process remains compact to achieve better placement performance. Experimental evaluations on mixed-cell-height benchmarks demonstrate that the proposed approach achieves smaller total displacement and notably lower HPWL variation within practical time limits compared with state-of-the-art legalization methods. Moreover, this work provides a scalable foundation for future extensions to three-dimensional (3D) IC placement legalization.

ElectronicsVol. 14(21)
Shenzhen University (CN)
Openalex Percentile: Top 68%
VLSI and FPGA Design Techniques
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Netlist-Aware Mixed-Cell-Height Legalization — Ting Liang, Bin Yih Liao, et al. · Electronics (2025) | TGRS Research Map | TGRS