Reliability of Fine-Pitch Cu-Microbumps for 3D Heterogeneous Integration: Effect of Solder, Pitch Scaling and Substrate Materials

A new and transformative era in semiconductor packaging is underway, wherein, there is a shift from transistor scaling to system scaling and integration through advanced packaging. For advanced packaging, interconnect scaling is a key driver, with interconnect density requirements for chip-to-substrate microbump pitch below 5 μm and half-line pitch below 1 μm for Cu redistribution layer (RDL). Here, we present a comprehensive theoretical comparison of thermal cycling behavior in accordance with JESD22-A104D standard, intermetallic thickness evolution, and steady-state thermal analysis of Cu-microbump assembly for different bonding materials and substrates. Bonding materials studied include solder caps such as SAC105 (Sn98.5Ag1.0Cu0.5), eutectic Sn-Pb (Sn63Pb37), eutectic Sn-Bi (Sn42Bi58), Pb95Sn5, Indium, and Cu-Cu TCB structure. Effect of substrates including Si, glass and FR-4 is evaluated for various microbump structures with varying pitches (85 µm, 40 µm, 10 µm, and 5 µm) on their fatigue life. Results indicate that for Cu-microbump assemblies at an 85 µm pitch. The Pb95Sn5 exhibits the longest predicted fatigue life (3267 cycles by Engelmaier and 452 cycles by Darveaux), while SAC105 shows the shortest (320 and 103 cycles). Additionally, the Cu-Cu TCB structure achieves an estimated lifetime of approximately 7800 cycles, which is significantly higher than all solder-based Cu-microbump assemblies. The findings contribute to advanced packaging applications by providing valuable theoretical references for optimizing solder materials and structural configurations.