FPGA Implementation of a CNN-Based Topological Trigger for HL-LHC

The implementation of convolutional neural networks in programmable logic, for applications in fast online event selection at hadron colliders, is studied. In particular, an approach based on full event images for classification is studied, including hardware-aware optimisation of the network architecture, and evaluation of physics performance using simulated data. A range of network models are identified that can be implemented within resources of current FPGAs, as well as the stringent latency requirements of HL-LHC trigger systems. A candidate model that can be implemented in the CMS L1 trigger for HL-LHC is shown to be capable of excellent signal/background discrimination for a key HL-LHC channel, HH(bbbb), although the performance depends strongly on the degree of pile-up mitigation prior to image generation.