Analysis of Representative Critical Path as Delay Line for Bundled-Data Circuits

Asynchronous Bundled-Data circuits are well-established for energy-efficient applications. A key requirement in such designs is an accurate delay matching between the data path and the associated delay lines, which becomes challenging due to increased sensitivity to process, voltage, and temperature variations, particularly for low-voltage regimes. This paper investigates delay lines based on Representative Critical Path as a robust alternative to traditional CMOS inverter-based chains. Implemented in STMicroelectronics 28 nm FDSOI technology, the proposed Representative Critical Path is evaluated for both Low-Voltage Threshold and Regular-Voltage Threshold transistors, which differ in energy-performance tradeoffs. A comprehensive analysis compares these structures across multiple process corners and a wide voltage range. Results show that the proposed Representative Critical Path delay line provides better tracking variability regarding the critical path across different corners, reducing the need for large delay margins by up to $10 \%$ and achieving approximately $30 \%$ energy savings.