Performance improvement of all-optical programmable logic array chip with loss-optimized silicon waveguides

Programmable logic array (PLA) based on canonical logic units (CLUs) can provide an effective way to realize optical digital computing by enabling arbitrary reconfigurable logic functions. Silicon-based all-optical PLA chips are promising candidates for practical applications due to their high speed and complementary metal oxide semiconductor (CMOS) compatibility. Here, we present an investigation optimizing the output performance of the silicon-based all-optical PLA chip monolithically integrating delay interferometers (DIs) and nonlinear waveguides. A comprehensive theoretical model is introduced to analyze how linear scattering and nonlinear absorption losses degrade the performance of output CLUs with high power penalty and extinction ratio (ER) reduction. By optimizing the ridge waveguide width, length, and bending geometry to reduce losses, theoretical investigation shows that 4.71 dB and 4.92 dB improvements in ER and output power of CLUs compared with conventional 500-nm-wide waveguides. A monolithic PLA chip with DIs and nonlinear waveguides is fabricated based on co-optimized waveguide geometry. A complete set of 50 Gb/s high-quality CLUs are developed simultaneously, and reconfigurable logic functions are further implemented through selective power coupling among CLUs. The proposed all-optical PLA chip can serve as a promising all-optical digital processor in future high-speed optical signal processing and computing systems.