An FFT Optimal Scaling Vector Search Scheme Based on Dynamic Programming

The fast Fourier transform (FFT) is widely used in digital signal processing. However, hardware implementations of the discrete Fourier transform (DFT)/FFT are limited by word length constraints, necessitating truncation, saturation, and scaling operations to balance hardware resources and computational performance. The choice of a suitable scaling vector significantly affects FFT efficiency. This paper introduces a novel estimation model for FFT error power, accounting for both quantization and saturation errors. Based on this model, we propose a dynamic programming (DP)‐based scaling vector search scheme to reduce the search space and computational complexity. After 1000 experiments, the model demonstrated a mean and variance of relative error in signal‐to‐noise ratio (SNR) of 0.063 and 0.35, proving its effectiveness. In a case study of a 1024‐point FFT, our model accurately estimated error power. While the exhaustive search yielded an optimal SNR of 65.91 dB, our method reduced the search space by 3600 times, with only a 0.3 dB loss in SNR. In a 256‐point FFT hardware implementation, performance improved by over 10 dB. Our scheme achieves SNR performance comparable to other methods when bit width is fixed and superior SNR when bit width is variable. This approach offers guidance for selecting scaling vectors in FFT hardware design.

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Publication Details

Journal
IET Circuits Devices & Systems
Published
2025-01-01
DOI
https://doi.org/10.1049/cds2/5773930
Primary Topic
Digital Filter Design and Implementation
Type
article
Field-Weighted Citation Impact
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article

An FFT Optimal Scaling Vector Search Scheme Based on Dynamic Programming

Jianhao Hu, Kaining Han, Yubin Zhu, Jinwei Xie
IET Circuits Devices & Systems
Digital Filter Design and Implementation
article

An FFT Optimal Scaling Vector Search Scheme Based on Dynamic Programming

Jianhao Hu, Kaining Han, Yubin Zhu, Jinwei Xie
article en

Abstract

The fast Fourier transform (FFT) is widely used in digital signal processing. However, hardware implementations of the discrete Fourier transform (DFT)/FFT are limited by word length constraints, necessitating truncation, saturation, and scaling operations to balance hardware resources and computational performance. The choice of a suitable scaling vector significantly affects FFT efficiency. This paper introduces a novel estimation model for FFT error power, accounting for both quantization and saturation errors. Based on this model, we propose a dynamic programming (DP)‐based scaling vector search scheme to reduce the search space and computational complexity. After 1000 experiments, the model demonstrated a mean and variance of relative error in signal‐to‐noise ratio (SNR) of 0.063 and 0.35, proving its effectiveness. In a case study of a 1024‐point FFT, our model accurately estimated error power. While the exhaustive search yielded an optimal SNR of 65.91 dB, our method reduced the search space by 3600 times, with only a 0.3 dB loss in SNR. In a 256‐point FFT hardware implementation, performance improved by over 10 dB. Our scheme achieves SNR performance comparable to other methods when bit width is fixed and superior SNR when bit width is variable. This approach offers guidance for selecting scaling vectors in FFT hardware design.

IET Circuits Devices & SystemsVol. 2025(1)
University of Electronic Science and Technology of China (CN)
Openalex Percentile: Top 60%
Digital Filter Design and Implementation
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