Fabrication of Dual Vertical C-Shaped-Channel Nanosheet FETs via a Novel Integration Process for High-Density, Scalable CMOS Applications

We present dual Vertical C-Shaped-Channel Nanosheet Field-Effect Transistors (dVCNFETs), with a novel integration process aimed at advancing the scalability and performance of future CMOS technologies. The proposed method leverages epitaxial Si/SiGe/Si layers, enabling precise control over gate length and channel thickness. By incorporating spacer image transfer (SIT) and bidirectional cross-etching (BCE) techniques, dual-channel structures are formed with self-aligned high-k metal gates (HKMG). The dVCNFETs demonstrate impressive electrical performance with an on-state current (Idsat) of 442 μA/μm, sub-threshold slope (SS) of 61.64 mV/dec, and a high Ion/Ioff ratio of 1.19 × 10., showcasing superior short-channel control and device scalability. This integration technique, which could fabricate multiple channels, compatible with state-of-the-art CMOS fabrication processes, holds significant potential for high-density integrated circuits and future advanced logic applications.