Cryogenic Current-Steering DAC Design and Validation Using Transistor Modeling Based on Physics-Inspired Residual Neural Network

This paper presents a method for designing a cryogenic current-steering digital-to-analog converter (CS-DAC), particularly in cases where cryogenic precise device models are unavailable. The proposed design method utilizes a physics-inspired residual multilayer perceptron (Phy-ResMLP) network to model the current-voltage (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I-V</i>) and mismatch characteristics of cryogenic transistor pairs in 28-nm technology. The Phy-ResMLP network comprises multilayer perceptron (MLP) based residual blocks and a physics-inspired loss function, which improves the model's interpretability and accuracy. The established model demonstrates a minimum root mean square error (RMSE) of only 0.95%, which is 27% lower than that of the state-of-the-art models. This model is then applied to design a 10-bit, 2GS/s CS-DAC, resulting in an average simulated differential non-linearity (DNL)/integral non-linearity (INL) of 1.03/2.34 LSB, with a standard deviation of 0.22/0.63 LSB, respectively. The average simulated spurious-free dynamic range (SFDR) is 50.39 dBc, with a standard deviation of 4.11 dBc. In addition, 10 fabricated CS-DACs in 28-nm technology are measured at 4K, with DNL ranging from 0.92 LSB to 1.15 LSB, INL from 2.18 LSB to 2.68 LSB, and SFDR from 49.4 dBc to 51.3 dBc. These measured values fall within the ±1-σ confidence interval of the simulated DNL/INL and SFDR based on the proposed cryogenic transistor model, with a mean error of less than 3%.