Establishment and modulation of linear VTH model with low interface states using atomic layer etching for E-mode GaN-based P-MOSFETs for digital logic application

In this work, the modulation effect of low interface states for threshold voltage (VTH) model of GaN-based p-channel metal-oxide-semiconductor field effect transistors (P-MOSFETs) is investigated. By using atomic layer etching, P-MOSFETs with low interface states and varying channel thickness (tch) were fabricated. Depending on the deposition of high quality Al2O3 as gate dielectric and improved interface states, enhancement-mode P-MOSFET with low off-state current (∼10−9 mA/mm) and high Ion/Ioff ratio (∼109) is obtained. Based on the experiment, the linear model between VTH and tch is established. Taking the effect of interface charges into account, the linear VTH model for P-MOSFETs is modulated positively with low interface states compared with inductively couple plasma method. This resulted in a reduced critical channel thickness of 8.5 nm to acquire enhancement operation for P-MOSFETs with low interface states in this work. The low interface states also contribute to improved performance of P-MOSFETs on on-resistance, saturation current and transconductance. Additionally, physical implications of the parameters in the linear VTH model are also investigated, theoretically demonstrating how interface states modulate VTH.