A Development of a Robust Computer Vision-based Framework for Metrology and Inspection of Stacked Die in HBM Process

The rapid advancement of high bandwidth memory (HBM) technology introduces significant challenges in metrology due to its complex 3D stacked die architecture. Conventional measurement and inspection tools, optimized for planar DRAM wafers, fail to accurately assess critical die-to-die alignment parameters such as die shift and tilt, particularly post-bonding. This paper presents a novel metrology methodology leveraging infrared (IR) imaging combined with advanced image processing algorithms to overcome these limitations. A dual-scan system captures both base wafer fiducials and top die patterns, enabling precise alignment measurement within stacked HBM assemblies. Edge enhancement using Sobel filtering and normalized cross-correlation (NCC) techniques facilitate robust pattern recognition and sub-pixel alignment, addressing challenges posed by low contrast and IR resolution constraints. Experimental validation on production-grade HBM wafers demonstrates superior recognition rates and measurement repeatability, establishing the proposed approach as a reliable and efficient solution for next-generation semiconductor metrology. The integration of IR optics and sophisticated algorithmic processing significantly improves inspection coverage, contributing to enhanced yield and manufacturing robustness in advanced 3D memory technologies.

Authors

Publication Details

Journal
JSTS Journal of Semiconductor Technology and Science
Published
2025-10-30
DOI
https://doi.org/10.5573/jsts.2025.25.5.484
Primary Topic
Advancements in Photolithography Techniques
Type
article
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article

A Development of a Robust Computer Vision-based Framework for Metrology and Inspection of Stacked Die in HBM Process

Sunghyun Yoon, Hyejeong Seong, Young‐Hoon Lee, G.S. Yoon
JSTS Journal of Semiconductor Technology and Science
Advancements in Photolithography Techniques
article

A Development of a Robust Computer Vision-based Framework for Metrology and Inspection of Stacked Die in HBM Process

Sunghyun Yoon, Hyejeong Seong, Young‐Hoon Lee, G.S. Yoon
article en

Abstract

The rapid advancement of high bandwidth memory (HBM) technology introduces significant challenges in metrology due to its complex 3D stacked die architecture. Conventional measurement and inspection tools, optimized for planar DRAM wafers, fail to accurately assess critical die-to-die alignment parameters such as die shift and tilt, particularly post-bonding. This paper presents a novel metrology methodology leveraging infrared (IR) imaging combined with advanced image processing algorithms to overcome these limitations. A dual-scan system captures both base wafer fiducials and top die patterns, enabling precise alignment measurement within stacked HBM assemblies. Edge enhancement using Sobel filtering and normalized cross-correlation (NCC) techniques facilitate robust pattern recognition and sub-pixel alignment, addressing challenges posed by low contrast and IR resolution constraints. Experimental validation on production-grade HBM wafers demonstrates superior recognition rates and measurement repeatability, establishing the proposed approach as a reliable and efficient solution for next-generation semiconductor metrology. The integration of IR optics and sophisticated algorithmic processing significantly improves inspection coverage, contributing to enhanced yield and manufacturing robustness in advanced 3D memory technologies.

JSTS Journal of Semiconductor Technology and ScienceVol. 25(5)
Openalex Percentile: Top 69%
Advancements in Photolithography Techniques
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