Scalability of 28-nm Ternary CMOS Technology Using Halo Profile for Low-leakage and High-density SRAM

We propose a highly scalable ternary CMOS (T-CMOS) technology using halo implantation in commercial 28-nm process. By forming a locally confined halo profile, VDS-dependent constant band-to-band tunneling (BTBT) current is successfully obtained which enables VDD-scalable subthreshold ternary operation. The merged halo profile near source/drain junction exhibits excellent short-channel behavior and facilitates the suppression of the tunneling current with a reduced ion dose than retrograde one, while maintaining the same VT design. Halo energy and tilt angle are introduced as additional design knobs to further reduce the tunneling current, expanding the T-CMOS design window. Therefore, low-power ternary operation is demonstrated in a wide-bias range from 1.0 V to 0.3 V, with sub-picoampere level leakage. By leveraging an additional VDD/2 latch state that enables 1.5-bits per cell storage in a high-density 6T bitcell, our T-SRAM achieves 0.62 pW/bit leakage power and nearly a 10× improvement in the figure-of-merit (cell density / leakage power) over prior reported low-leakage SRAMs.