Industry’s First In-line Chip Warpage Measurement Methods for HBM Manufacturing Using UV-In Delamination and a Flux-based Support Layer

Advanced Packaging (AP) is driving innovation beyond the limits of traditional Moore’s Law scaling. Among various advanced packaging technologies, High-Bandwidth Memory (HBM) is gaining significant attention for next-generation semiconductors. As the number of stacked layers in high-bandwidth memory increases, wafer and chip warpage become critical quality factors directly impacting yield and reliability. However, there is currently no equipment or method for direct in-line measurement of chip warpage, as ultra-thin wafers are bonded to carrier wafers during handling, making warpage measurement in this state meaningless. This paper presents the world’s first research on a direct, large-scale, non-destructive chip warpage measurement process applicable in in-line manufacturing. We developed a novel measurement method based on specialized process treatments and hardware modifications. Experimental validation confirmed the accuracy and reliability of the proposed approach. The resulting high-volume chip-level warpage data showed a strong correlation with actual measurements, demonstrating that the method provides highly meaningful data for mass production applications. The results of this study have been implemented into measurement equipment and developed into a commercialized solution currently in use.