TEOS SiO₂ Film Deposition Optimization for Increasing Capability and Securing TSV Robustness of HBM

At SK hynix’s wafer level package (WLPKG) line, a passivation SiN layer is deposited to prevent Cu diffusion in through silicon via (TSV), followed by a tetraethyl orthosilicate (TEOS)-based SiO₂ layer deposition to ensure TSV robustness during planarization of protruded TSVs. With the increasing demand for high bandwidth memory (HBM), the TEOS SiO₂ deposition process became a throughput bottleneck due to the chamber configuration of the existing CVD equipment. To enhance productivity, process optimization was pursued to improve the deposition rate while maintaining the film properties required for subsequent processes. Recipe modifications were evaluated under mass production conditions, with a focus on deposition rate, film uniformity, and potential risks such as particle generation and CMP removal rate (R/R) changes that could impact TSV yield. Increasing TEOS flow initially improved the deposition rate by up to 78% but caused TSV damage due to higher CMP R/R at wafer edges. By optimizing O₂ flow, He-carrier flow, and chamber pressure, film robustness was enhanced, and final adjustments reduced TEOS flow to achieve a 46% rate improvement without significant R/R variation. The optimized recipe increased CVD process capacity by approximately 25%, meeting both productivity and quality stability requirements for high-volume HBM manufacturing.