Simple True Random Number Generator Using Capacitive Oscillators for FPGA Implementation

The need for unpredictable sequences of bits is common in many important security applications. These sequences can only be generated by true random number generators (TRNGs). Apart from the natural analog domain for TRNGs, this type of generator is also required as a digital-based solution, particularly leveraging field-programmable gate array (FPGA) platforms. Despite the number of existing FPGA-based implementations, new solutions that use different types of entropy sources, utilize fewer FPGA resources, or ensure higher throughput are still being sought. This paper presents an architecture of a simple TRNG targeted for implementation in FPGAs. As a source of entropy, the TRNG exploits jitter in capacitive oscillators and metastability in flip-flops. The capacitive oscillators, in turn, use the input–output cells of an FPGA chip and unconnected external pins and cyclically charge and discharge the parasitic capacitance associated with these pins. The TRNG needs a small number of FPGA resources, namely 13 look-up tables (LUTs), 12 flip-flops, and 3 unused pins. Its throughput is approximately 12.5 Mbit/s for AMD/Xilinx Artix-7 FPGA family chips. The presented TRNG passes all the NIST statistical tests for a wide range of operating conditions.