Design of a variable digital filter based on all pass transformation with low-power modified conventional full adder and low-power Wallace tree multiplier to eliminate noise from sensor nodes

Variable digital filters (VDF) are essential components in digital signal processing, which find applications in audio processing and telecommunications. Current VDF designs often face challenges in delay, area consumption, and power efficiency. In this manuscript, design of all pass transformation fed variable digital filter using low power modified conventional full adder and low-power Wallace tree multiplier (APT-VDF-LPMCFA-LPWTM) is proposed. The proposed design is utilised for enhancing the filter efficiency by reducing noise in the sensor nodes. The proposed low power modified conventional full adder (LPMCFA) design is incorporated with carry prediction. Moreover, the proposed LPWTM is used for minimising the design complexity and power utilisation. The proposed filter attains 26.58%, 12.3%, 16.41% and 38.07% lower delay than the existing designs, FIR-Rdx2-LCSLA, FIR-RCA-VM, FIR-VL-CSKA-BM and PPA-VDRCA-FIR-ECG respectively. Simulation results of the proposed filter show improved noise reduction and reduced power consumption compared to conventional designs.