Atomic layer etching for vertical trench control and electrical optimization in high-density low-k materials

As device scaling continues, it becomes increasingly challenging to enhance device performance. In order to improve device performance, reducing resistance and capacitance in the Back-End of Line (BEOL) is especially important. Among various methods, minimizing damage to low-k dielectric materials during patterning processes has become a key challenge in BEOL integration. In this work, we suggest using Atomic Layer Etching (ALE) to overcome this problem, along with the selection of suitable low-k materials. ALE enhances controllability over surface reactions and profile formation by utilizing low ion energy, which enables the achievement of vertical profiles while simultaneously minimizing Plasma-Induced Damage (PID). The proposed ALE process utilizes a fluorocarbon-based surface modification step (C4F8), followed by a low-energy O2 plasma step for selective carbon removal. This cyclic approach enables atomic-scale material removal with minimal physical damage, significantly reducing ion bombardment effects. To evaluate the effect of ALE on different low-k materials, we tested various high-density low-k samples with differences in the k-value, modulus, and carbon composition. The process performance was evaluated through detailed compositional analysis (XPS), PID characterization, and electrical measurements. The results confirmed that the proposed ALE method effectively reduced damage to one of the tested low-k materials while systematically enhancing profile control. Consequently, it demonstrates strong potential as a next-generation patterning solution for advanced BEOL integration.