Low-Power Radix-22 FFT Processor with Hardware-Optimized Fixed-Width Multipliers and Low-Voltage Memory Buffers

In this paper, we propose a novel low-power implementation of the radix-22 Fast Fourier Transform (FFT) processor that exploits optimized multiplications and low-voltage memory buffers. The FFT computation requires complex products between input samples and precomputed coefficients, known as twiddle factors, as well as a large number of memory elements to store intermediate signals. To reduce power consumption, we bypass multiplications when twiddle factors are equal to zero or one. Furthermore, we introduce a fixed-width technique that lowers multiplier complexity for non-trivial coefficients by pruning the least significant columns of the partial product matrix and discarding the most significant partial products with low activation probability. To further minimize power consumption, we lower the supply voltage of memory buffers, creating two power domains in the design. Post-synthesis analysis in 28 nm technology shows that the proposed FFT achieves superior SNR and MSE compared to existing implementations, with reductions of 33% in power consumption and 30% in the power-delay product. In an OFDM receiver, the design also achieves optimal bit error rate performance under various levels of channel noise.