Impact of interface traps on the subthreshold performance of InGaAs nanosheet transistors

The performance of InGaAs based transistors can be significantly affected by the presence of interface traps, particularly in the subthreshold regime. In this study, the role of such defects has been investigated through the fabrication and the characterization of MOSCAP structures and nanosheet transistors. TCAD simulations have been used to extract interface-trap densities. Results reveal that the distributed defect tail into the bandgap is ∼ 5 × 10 11 cm − 2 eV − 1 and degrades the subthreshold slope of about 39%, while interface traps inside the conduction band limit g m MAX to 561 μ S/ μ m. The study emphasizes the need for improved interface engineering to unlock the full potential of nanoscale InGaAs-based devices. • Fabrication of InGaAs MOSCAPs and nanosheet transistors. • Extraction of interface traps in InGaAs. • TCAD simulations link trap states to subthreshold slope degradation. • Traps identified as key limiters of electrostatic control in scaled InGaAs devices. • Agreement with measurements confirms validity of the physics-based trap distribution. • Enables interface optimization strategies to improve InGaAs device scalability.