Low-Power Differential Flip-Flop Using Clock Gating for Energy-Efficient Applications

The Static Contention-Free Differential Flip-Flop (SCDFF) is a robust flip-flop design known for its fully static operation and differential logic structure, offering low-power and high-speed performance. However, its reliability and efficiency degrade under Process, Voltage, and Temperature (PVT) variations and dynamic workload conditions. This paper proposes an enhanced architecture Adaptive Threshold-Controlled SCDFF (ATC-SCDFF) to overcome these limitations. The ATC-SCDFF integrates adaptive body biasing (ABB), dual-mode clock gating, a differential sleep transistor network, and skew-tolerant delay balancing to achieve improved power-performance trade-offs. Adaptive Body Biasing dynamically adjusts the threshold voltage through Forward Body Bias (FBB) and Reverse Body Bias (RBB), depending on workload activity. Dual-mode clock gating reduces unnecessary clock transitions using input-data change detection. The differential sleep network ensures symmetric power gating and metastability resistance, while delay balancing maintains signal integrity across the differential clock paths. The design was implemented and simulated using Tanner EDA v16.0, demonstrating a 22% reduction in average power, 11% improvement in propagation delay, 30% lower leakage, and 22% lower energy consumption compared to conventional SCDFF, with only a 6% area overhead. These results confirm the ATC-SCDFF’s effectiveness for reliable and energy-efficient flip-flop operation in advanced digital systems.