A 0.13- <i>μ</i> m HV CMOS Fully-Integrated Galvanic Isolator for Gate Drivers With Asynchronous Full-Duplex Communication
This article presents a fully-integrated galvanic isolator for gate drivers with asynchronous full-duplex communication. Amplitude-shift keying (ASK) and load-shift keying (LSK) are deployed to simultaneously transmit data in the two directions of communication. A symmetric data rate of 66.7 Mb/s is achieved in a completely asynchronous communication scenario, without the need for a reference clock. The two transceivers are fabricated in a 0.13-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula>m HV CMOS technology, covering an area of 2.2 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The data link ensures full-duplex data transfer with a BER below <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{-6}$</tex-math> </inline-formula> and a propagation delay always lower than 20 ns. The power consumption from the low 1.5-V supply amounts to 5.75 mW.
Authors
- Andrea Bevilacqua (ORCID: https://orcid.org/0000-0002-5664-9197)
- A. Neviani (ORCID: https://orcid.org/0000-0002-7839-9192)
- Karl Norling
- Lucrezia Navarin (ORCID: https://orcid.org/0009-0009-5073-6423)
- Marco Parenzan (ORCID: https://orcid.org/0009-0005-5773-8852)
- Alexander Uran
- Stefano Ruzzu (ORCID: https://orcid.org/0009-0005-1722-5630)
- Krithika Rathinam
Institutions
- University of Padua (IT)
- Infineon Technologies (Austria) (AT)
Publication Details
- Journal
- IEEE Journal of Solid-State Circuits
- Published
- 2025-01-01
- DOI
- https://doi.org/10.1109/jssc.2025.3619878
- Primary Topic
- Analog and Mixed-Signal Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.00