A 0.13- <i>μ</i> m HV CMOS Fully-Integrated Galvanic Isolator for Gate Drivers With Asynchronous Full-Duplex Communication

This article presents a fully-integrated galvanic isolator for gate drivers with asynchronous full-duplex communication. Amplitude-shift keying (ASK) and load-shift keying (LSK) are deployed to simultaneously transmit data in the two directions of communication. A symmetric data rate of 66.7 Mb/s is achieved in a completely asynchronous communication scenario, without the need for a reference clock. The two transceivers are fabricated in a 0.13-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula>m HV CMOS technology, covering an area of 2.2 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The data link ensures full-duplex data transfer with a BER below <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{-6}$</tex-math> </inline-formula> and a propagation delay always lower than 20 ns. The power consumption from the low 1.5-V supply amounts to 5.75 mW.

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Publication Details

Journal
IEEE Journal of Solid-State Circuits
Published
2025-01-01
DOI
https://doi.org/10.1109/jssc.2025.3619878
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
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article

A 0.13- μ m HV CMOS Fully-Integrated Galvanic Isolator for Gate Drivers With Asynchronous Full-Duplex Communication

Andrea Bevilacqua, A. Neviani, Karl Norling, Lucrezia Navarin et al.
IEEE Journal of Solid-State Circuits
Analog and Mixed-Signal Circuit Design
article

A 0.13- μ m HV CMOS Fully-Integrated Galvanic Isolator for Gate Drivers With Asynchronous Full-Duplex Communication

Andrea Bevilacqua, A. Neviani, Karl Norling, Lucrezia Navarin, Marco Parenzan, Alexander Uran, Stefano Ruzzu, Krithika Rathinam
article en

Abstract

This article presents a fully-integrated galvanic isolator for gate drivers with asynchronous full-duplex communication. Amplitude-shift keying (ASK) and load-shift keying (LSK) are deployed to simultaneously transmit data in the two directions of communication. A symmetric data rate of 66.7 Mb/s is achieved in a completely asynchronous communication scenario, without the need for a reference clock. The two transceivers are fabricated in a 0.13-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula>m HV CMOS technology, covering an area of 2.2 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The data link ensures full-duplex data transfer with a BER below <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{-6}$</tex-math> </inline-formula> and a propagation delay always lower than 20 ns. The power consumption from the low 1.5-V supply amounts to 5.75 mW.

IEEE Journal of Solid-State Circuits
University of Padua (IT), Infineon Technologies (Austria) (AT)
Openalex Percentile: Top 70%
Analog and Mixed-Signal Circuit Design
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A 0.13- <i>μ</i> m HV CMOS Fully-Integrated Galvanic Isolator for Gate Drivers With Asynchronous Full-Duplex Communication — Andrea Bevilacqua, A. Neviani, et al. · IEEE Journal of Solid-State Circuits (2025) | TGRS Research Map | TGRS