A Temperature and Common-Mode Insensitive 8.6 bit 1.5 GS/s Pipelined SAR ADC Using Complementary Dynamic Amplifier in 28 nm CMOS

This article presents an 8.6-bit 1.5GS/s input common-mode voltage (V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">INCM</sub>) and temperature insensitive pipelined successive approximation register (SAR) analog-to-digital converter (ADC). It consists of 5-stage sub-SAR ADC with 2b+2b+2b+2b+3b resolution including redundancy bits where a complementary dynamic amplifier (CDA) is used as a residue amplifier (RA) in the first 4 stages. Furthermore, it also includes a V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">INCM</sub>-aware reset voltage generation and an on-chip temperature-sensor-based stage gain compensation scheme for the CDAs to realize robust operation over a wide range of V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">INCM</sub> and temperatures. The ADC is fabricated in 28nm CMOS technology and attains signal-to-noise-and-distortion-ratio (SNDR) of 49.35dB and spurious-free-dynamic-range (SFDR) of 64.50dB at Nyquist input frequency. The power consumption of the ADC core is 8.22mW, which corresponds to Schreier figure of merit (F<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</sub>M) of 158.95dB. It operates reliably over V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">INCM</sub> variation of 112mV and a temperature variation of 100°C, even while using many pipeline stages, and occupies a core area of 0.0306mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.