Design and Analysis of Self Recoverable Triple Node Upset Hardened Latch With Novel Triple Input-Dual Output C-Element for Aerospace Applications

Designing fault resilient storage components is a significant challenge in radiation-hardened systems, as CMOS scaling causes systems to be more susceptible to radiation-induced Multiple-Node Upsets (MNUs). The proposed Triple input-Dual output C-element-based Triple Node Upset Self-Recoverable Latch (TDCTRL)improves Triple Node Upset(TNU)recovery fault injections with reduced complexity and improved reliability. To achieve optimal self-recovery from all TNU cases, the design employs the most innovative Triple input-Dual output C-element (TDCs) based, which ultimately reduces area overhead by using three TDCs, three clocked TDCs, and independently driven outputs. The proposed TDCTRL provides exceptional radiation tolerance. Power consumption and delay penalties are substantially reduced through the utilisation of an optimised high-speed path and reliable performance in the context of voltage and temperature changes. Simulation results show that the TDCTRL performs more effectively than other traditional TNU self-recovery latches, reduces delay by 49.68%, power delay product by 25.84% and area power delay product by 28.24% compared to the best TNU resilience latch reported in the literature.