Design of 30 nm negative capacitance FinFET using PZT for high-speed processors

FinFETs are promising candidates for reduced transistor dimensions, showing a high switching current ratio and better subthreshold performance. It shows better gate control over the channel due to multiple gates, including side and top gates. There is scope for improvement in FinFET performance for sub-30 nm technology nodes, exploring new oxide materials with ferroelectric properties. Ferroelectric material shows negative capacitance properties that reduce the subthreshold slope with steep subthreshold performance. In this work, a 30 nm negative capacitance FinFET (NC-FinFET) is designed and analyzed for electrostatic and switching performance for low-power applications. PZT (Pb(ZryTi1−y)O3) is one of the promising ferroelectric materials that was used for the performance improvement of NC-FinFET with multi-fin architecture. There are improvements in the Ion/Ioff switching current ratio, subthreshold performance parameters and transconductance of the proposed NC-FinFET. The electric field and surface potential of NC-FinFET also show sharp variations compared to the conventional FinFET. The proposed device is analyzed for doping variations of source, drain and channel as well as gate material impact, along with and without ferroelectric material. The use of PZT near its morphotropic phase boundary (y = 0.52) ensures optimized polarization, enabling subthreshold slope improvement and enhanced ON/OFF current ratio. The proposed device achieves a reduced subthreshold slope of 60.17 mV/dec, a higher Ion/Ioff ratio of 10¹⁰ and lower static power consumption (~ 0.0003 nW) with high switching performance and better electrostatic properties, validating its suitability for low-power, high-speed processors, logic and memory-centric applications. The proposed design was carried out using the 3D Visual TCAD tool provided by Cadre Design System.