Enhancing fault-tolerant application mapping in network-on-chip through transformer network based reinforcement learning approach

Abstract Network-on-Chip (NoC) is a promising technology that uses a network of interconnected processing elements to improve performance and reduce communication costs in complex systems. However, faults can occur in NoC systems due to various factors such as manufacturing defects, aging, and environmental factors. To address this challenge, fault-tolerant techniques are necessary to ensure the reliable and efficient operation of NoC systems. One such technique is fault-tolerant application mapping, in which application cores are assigned to processing elements to reduce the system performance degradation caused by the failures. However, the application mapping for NoC systems, including fault tolerance, is a complex task. This paper presents a novel approach consisting of a transformer-based reinforcement learning algorithm for application mapping in mesh topology based NoC. This allows NoC to communicate efficiently in the presence of faults. The proposed approach is compared with other state-of-the-art techniques. The findings demonstrate that the proposed approach outperforms the average communication cost encompassing 2, 5, and 7 percent more than RL-MAP, NMA, and PSO, respectively, and also has less run-time. Also, it is observed that the introduced technique excels against the remaining techniques with respect to the average network latency decrease by 3, 5, and 6 percent for RL-MAP, NMA, and PSO correspondingly. The approach in this method is thus helpful in the design of NoC systems that are energy efficient as well as reliable for targeted applications.