Machine Learning‐Based Standard Compact Model Binning Parameter Extraction Methodology for Integrated Circuit Design of Next‐Generation Semiconductor Devices

This article proposes a neural network‐based parameter extraction methodology for the Berkeley Short‐Channel IGFET Model–Common Multi‐Gate (BSIM–CMG) model applied to gate‐all‐around field effect transistors (GAAFETs), capturing both current–voltage and capacitance–voltage characteristics to support compact model library development. Conventional BSIM parameter extraction is often complex and inefficient, requiring manual intervention and significant time to cover a wide range of device dimensions and temperatures. To address these limitations, a novel binning adaptive sampling strategy is integrated into the neural network‐based extraction framework to efficiently generate training data across broad device dimension ranges. In addition, the transformer‐based deep neural networks are designed to output only binnable parameters, ensuring compatibility with compact model library requirements. The trained networks are tested using 3 nm node GAAFET Technology Computer Aided Design (TCAD) data under various conditions, achieving mean absolute percentage errors below 5% for both drain current and gate capacitance. Consequently, the extracted parameters are integrated with corner model parameters through binning equations. This approach results in binning models that are readily deployable in compact model libraries while significantly reducing parameter extraction time and enabling automation across a wide range of GAAFET dimensions.