Exploring Microscaling MX Minifloat Systolic Arrays on FPGAs

The rapid advancement of generative AI and exponential growth of model parameters has driven the pursuit of alternative arithmetic formats to enhance efficiency while maintaining inference accuracy. While earlier efforts to implement small floating point formats (minifloats) have been somewhat ad-hoc, the Microscaling MX formats proposed by the Open Compute Project offer a standard around which hardware designers can converge. This article explores the design space of systolic array architectures for Microscaling MX formats on FPGAs. It provides a detailed analysis of the area and timing characteristics of systolic arrays implemented on AMD UltraScale+ FPGAs for 6-bit and 8-bit MX formats, exploring different accumulation and pipelining strategies while maintaining high computational throughput. Our most optimized design reaches a peak throughput of 568 GOPS using 4-stage and 3-stage pipelined Exact accumulation for MXFP6 E3M2 and E2M3, respectively.