VLSI Implementation of High‐Speed and Area‐Efficient Multiplierless Address Generation Architecture for Deinterleaver in WiMAX Applications

This paper presents a VLSI implementation of a high‐speed, area‐efficient, multiplierless address generation architecture for the WiMAX deinterleaver, conforming to the IEEE 802.16e standard. The primary motivation of this work is to reduce hardware complexity and delay by eliminating multipliers, which are traditionally used in address generation. The proposed architecture is designed for FPGA and ASIC platforms, emphasizing simplicity, reduced latency, and efficient hardware utilization. The design supports standard modulation schemes—QPSK, 16‐QAM, and 64‐QAM—with their respective code rates. Two key performance evaluations were conducted: Score 1, which refers to FPGA implementation on the Xilinx XC3S400, demonstrated a 13% increase in speed, and Score 2, based on ASIC analysis using 45‐nm CMOS technology, and achieved improvements of 17% in power delay product (PDP) and 22% in area delay product (ADP) over existing architectures. These results confirm the architecture’s effectiveness for high‐speed, low‐power applications in modern communication systems.