Innovative Approaches to Addressing Challenges in 3D Macro Placement

Macro placement is a critical step in 3D integrated circuit (IC) designs due to the challenges posed by the large size of macros and the presence of obstacles in certain areas. Previous research in 3D placement often simplifies macro validation based on prototyping outcomes. However, this approach may result in macros being placed far from their intended locations, leading to longer wire lengths and increased Through-Silicon Vias (TSVs). To tackle these challenges, this paper introduces a novel approach called K-tier Partially Occupied Corner Stitching (K-POCS). This method aims to determine optimal and permissible 2D positions for movable macros on a projection plane early in the design phase, which are then fixed permanently in place. Building on this concept, we propose two distinct design flows for managing 3D macro placement: the Partitioning Last Macro Flow (PL-MF) and the Partitioning First Tier Reassignment (PF-TR). In our experiments, we compare the effectiveness of different macro placement flows. The results consistently demonstrate that the PF-TR approach achieves superior outcomes. This success is attributed to its effective utilization of various placement strategies.