Two-stage op-amp with a low-voltage cascode load

A two-stage operational amplifier in 0.18-μm CMOS is presented to address the gain-swing trade-off in low-voltage designs. By employing an optimized low-voltage cascode current mirror as the active load, the proposed architecture achieves both high output impedance and wide voltage swing. Verified by post-layout simulations at 1.8 V, the op-amp exhibits a high gain of 95.51 dB, a slew rate of 75.76 V/μs, and excellent CMRR/PSRR above 95 dB, validating its effectiveness for high-performance analog applications. The design's robustness is validated across −40°C to 125°C and TT/SS/FF process corners, showing stable DC and large-signal performance despite layout-induced bandwidth degradation. Power consumption remains low and consistent across all conditions.