N-polar AlN-based enhancement-mode transistor with p-NiO <i> _x </i> gate stacks and reduced buffer trapping

Abstract N-polar AlN-based III-nitride enhancement-mode transistors on sapphire with GaN channels and p-type NiO x gate stacks are demonstrated. The devices feature a threshold voltage of +0.9 V, an on-off current ratio of ∼10 7 , and a subthreshold swing of 90 mV dec −1 , reflecting exceptional carrier confinement and resulting in robust gate control. Due to the thick AlN buffer acting as back-barrier, the two-dimensional electron gas is fully confined to the ∼5 nm GaN channel layer which suppresses buffer trapping, reducing the current collapse by ∼4.5× and the dynamic on-resistance degradation by ∼4× when measured alongside commercial III-polar enhancement-mode p-GaN gated high-electron-mobility transistors. Furthermore, extended on-state gate-drain stress (12 h at V GS = + 3 V, V DS = + 5 V) induces a low threshold voltage shift of only +0.3 V. This work establishes this novel N-polar GaN/AlN on sapphire transistor as a promising next generation technology platform, with performance poised to improve through further epitaxial and device-level optimisation.