Migration Using Context Cache for Multicore RISC‐V Processor

ABSTRACT With the advancement of computer technology, modern systems increasingly run multiple programs. A context switch occurs when the operating system switches the executing program from one thread to another. During this process, the system saves the current thread's context to memory and restores the context of the following thread from memory. However, the context switch has significant overhead, which can degrade overall system performance if it occurs frequently. In this study, we design the context cache for a multicore RISC‐V processor to reduce the migration overhead caused by context switches between multiple cores. By utilizing a context cache, we aim to accelerate context switches and improve system performance and efficiency. We evaluated the context cache, which reduced the overhead of thread migration. Furthermore, we assessed the trade‐off between performance and area by changing its configuration.

Authors

Institutions

Publication Details

Journal
Concurrency and Computation Practice and Experience
Published
2025-10-22
DOI
https://doi.org/10.1002/cpe.70342
Primary Topic
Human Pose and Action Recognition
Type
article
Field-Weighted Citation Impact
0.00
Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

Migration Using Context Cache for Multicore RISC‐V Processor

Kazutoshi Suito, Tsutomu Itou, Nobuyuki Yamasaki, Akira Yamazawa
Concurrency and Computation Practice and Experience
Human Pose and Action Recognition
article

Migration Using Context Cache for Multicore RISC‐V Processor

Kazutoshi Suito, Tsutomu Itou, Nobuyuki Yamasaki, Akira Yamazawa
article en

Abstract

ABSTRACT With the advancement of computer technology, modern systems increasingly run multiple programs. A context switch occurs when the operating system switches the executing program from one thread to another. During this process, the system saves the current thread's context to memory and restores the context of the following thread from memory. However, the context switch has significant overhead, which can degrade overall system performance if it occurs frequently. In this study, we design the context cache for a multicore RISC‐V processor to reduce the migration overhead caused by context switches between multiple cores. By utilizing a context cache, we aim to accelerate context switches and improve system performance and efficiency. We evaluated the context cache, which reduced the overhead of thread migration. Furthermore, we assessed the trade‐off between performance and area by changing its configuration.

Concurrency and Computation Practice and ExperienceVol. 37(25-26)
Keio University (JP), Shell (Japan) (JP)
Openalex Percentile: Top 70%
Human Pose and Action Recognition
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.

Migration Using Context Cache for Multicore RISC‐V Processor — Kazutoshi Suito, Tsutomu Itou, et al. · Concurrency and Computation Practice and Experience (2025) | TGRS Research Map | TGRS