20 MeV·cm²/mg Linear Energy Transfer Radiation Tolerant Six-Transistor Static-Random-Access-Memory Cell in 28 nm CMOS Technology

This paper presents the complete design and electrical simulations of a volatile memory cell in 28 nm CMOS bulk technology resistant to Single Event Upset at 20 $\mathrm{MeV} \cdot \mathrm{cm}^{2} / \mathrm{mg}$ of Linear Energy Transfer. The circuit topology of the cell is based on a classic six-transistor structure, in which the storage latches have a feedback impedance which allows to reduce the current contribution on the pull-down/pull-up network in case of upset events, avoiding unwanted setup of the stored bit. To demonstrate the robustness of the cell against upset events, the current pulse signal generated by the incident particles passing through the silicon substrate was modelled and generated by MATLAB equations and subsequently moved to SPICE environment simulator for performance verification. In the presence of an incident charge pulse of $\mathbf{1 5. 5 ~ f C}$ (whose duration is of the order of $\mathbf{4 0 0 ~ p s}$) the single event current pulse has a peak of $60 \mu \mathrm{~A}$ and generates a voltage variation of -250 mV with respect to the ‘ 1 ‘ logic value (0.9 V as nominal supply voltage for Standard Process MOS Transistors in 28 nm CMOS) with a recovery time below 1% of 0.9 V of only 600 ps. The simulations were carried out assuming to operate in a SRAM bank of 32 words of 32 bits, thus including the capacitive effects of the bit-line routing. The cell operates with $\mathbf{1 0 ~ n s}$ per operation (for the READ, WRITE and HOLD states, respectively) and has an energy/bit of $\mathbf{1 0 8} \mathbf{f J}, \mathbf{6 4} \mathbf{f J}$ and $\mathbf{1 2 6} \mathbf{f J}$, for the WRITE, HOLD and READ operations, respectively.